// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2006 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Lattice Semiconductor Corporation
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//                     TEL: 1-800-Lattice (USA and Canada)
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//                     web: http://www.latticesemi.com/
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// --------------------------------------------------------------------
//
//  Project:           7:1 LVDS Video Interface
//  File:              LVDS_7_to_1_TX_sapphire.v
//  Title:             LVDS_7_to_1_TX_sapphire
//  Description:       Tx module of this reference design for Sapphire architecture
//
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Ver: | Author   | Mod. Date  | Changes Made:
// V1.0 | shossner | 2010-04-25 | Initial Release
// V1.1 | shossner | 2010-11-03 | Accomodation for IPexpress module update
//
// --------------------------------------------------------------------

`timescale 1 ns/ 1 ps

module LVDS_7_to_1_TX 
     (
      RST_Tx  ,
              
      T0_in   ,
      T1_in   ,
      T2_in   ,
      T3_in   ,
              
      eclk    ,
      clk_s   ,
      stop    ,
      TCLK_out,
      T0_out  ,
      T1_out  ,
      T2_out  ,
      T3_out  
    );

   input        eclk;     // Tx module 3.5x clock 
   input        clk_s;    // slow clock for reset circuit
   input        stop;     // eclksync control signal 
   input        RST_Tx;   // Tx module reset
     
   input  [6:0] T0_in;    // 7-bit parallel data
   input  [6:0] T1_in;    // 7-bit parallel data
   input  [6:0] T2_in;    // 7-bit parallel data
   input  [6:0] T3_in;    // 7-bit parallel data
   
   output       TCLK_out; // LVDS clock output pair 
   output       T0_out;   // LVDS data output pair 0
   output       T1_out;   // LVDS data output pair 1
   output       T2_out;   // LVDS data output pair 2
   output       T3_out;   // LVDS data output pair 3


   wire   [3:0] tx_do;    // 4 serialized output data streams
   wire         reset;

assign reset = RST_Tx || stop  /* synthesis syn_keep = 1 */;


//--------------------------------------------------------------------
//-- IPexpress GDDR_7:1 Tx module
//--------------------------------------------------------------------
        
    ip_gddr71tx LVDS_71_Tx (
            .clkout     (TCLK_out), 
            .ready      (), 
            .refclk     (eclk), 
            .sclk       (), 
            .start      (1'b1), 
            .sync_clk   (eclk),
            .sync_reset (reset), //stop),
            .data0      (T0_in), 
            .data1      (T1_in), 
            .data2      (T2_in), 
            .data3      (T3_in), 
            .dout       (tx_do)
        );
    
//-----------------------------------
        

   assign T0_out = tx_do[0];
   assign T1_out = tx_do[1];
   assign T2_out = tx_do[2];
   assign T3_out = tx_do[3];



endmodule


